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claim it s the royal road, only one road. I ve made mistakes and so will you, and every consulting project has rough edges and setbacks. There is no such thing as a flawless consultant or perfect consulting, at least not in this world. Our lives are about success, not perfection. I ve chosen to reference my own works where relevant in the footnotes, but every chapter will conclude with suggested reading by another author whose work I deem appropriate, supportive, and enriching for the subjects discussed (with the rare exception of when one of my books has no peer on that subject). Think of them as the wine selections the captain offers with your meal. The only things that matter are results. I m confident that you can improve your ability to generate dramatic results immediately if you simply utilize the techniques in this book that appeal to you and apply to your environment. In that case, we ve both done our jobs. Alan Weiss, Ph.D. East Greenwich, RI October 2002

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group of memory transistors. The operation of this approach to flash memory will be described with the assistance of Figure 3.37 and Table 8.6. The program operation depends on uniform tunneling from the substrate to the floating gate. In the DiNOR array, this is accomplished by applying a bias of 10 V to the gate while the source line and the p well are biased at -9 V. The select gate is also biased at -9 V to prevent any current flow through the memory transistors. A triple-well process is used to split the potential difference and avoid applying more than 10 V bias across the junction in any well. In the selective erase mode, the word line of the selected row is biased at -9 V. The select gate is bias at 10 V to allow access to the memory transistors. Figure 8.38 shows the erase conditions within a pati al array. Those transistors that are to be erased have 6 V applied to their bit lines. These transistors will be erased to a conducting state, "0", by tunneling of electrons from the floating gate to the drain. The cell on WL0 that is connected to MBL1 has 0 Von the drain. This results in a lower field across the oxide between floating-gate and drain so that the tunneling current is reduced to such a small valte that this cell remains programmed to a nonconducting, "1," state. Because the low threshold voltage erased state is the state that is selectively written, the DiNOR operation is able to tighten the threshold distribution by the

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