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Changing the requirement to now eliminate Pb from electronic packages translates to a change in all of the preceding This change stems from an inherent difference in the physical and metallurgical properties and hence, the processibility and reliability of the two solder materials SnPb is an eutectic composition of its two parent elements, and has a melting temperature of 183 C Lead-free solder alloys, almost regardless of their type and composition, have a higher melting point Further, most of the lead-free compositions are not eutectic in nature, meaning that they do not melt at one temperature Instead, such compositions have a softening range of temperature Additionally, the higher melting/softening temperature imposes additional requirements on the assembly materials and on the assembly process For example, because of the higher solder reflow temperatures for Pb-free solders, the substrates must be able to maintain their integrity and withstand a higher temperature.

The flux used in the flip-chip assembly process now needs to be more aggressive in order to be effective on Pb-free solders and must not burn off at higher temperatures that correspond to the higher melting temperatures of Pbfree solders, while simultaneously leaving behind a residue that is not corrosive The underfill also needs to be suitably selected so that its chemistry is compatible with the flux residue Additional challenges are due to the fact that it is difficult to change all components on a system, all at a time, to lead-free Consequently, the industry must cope with a scenario where a system has mixed metallurgy partly SnPb based and the others Pb-free on the system boards..

4.3 SYSTEM-ON-A-CHIP (SOC) VERSUS SYSTEM-ON-A-PACKAGE (SOP)

For decades, the most efficient way to add more functions to an electronic system has been to integrate more functions on a chip either by reducing minimum line width, increasing the size of the chip, or both. Recently, however, it is beginning to be recognized that on-chip integration poses several practical challenges as the die size grows to increasing proportions. With increasing die size, the die-per-wafer yield at the wafer fabrication starts going down, partly due to the increased complexity, but also due the challenges in the wafer manufacturing processes.

FIGURE 13.3 Signal velocity as a function of dielectric constant. (Prepared by Shared Resources, Inc., 1991.)

eliminates both drilling and plating. The substrate material system is often resin impregnated paper, the lowest-cost substrate system for electronic packaging. Summarizing, successful RF and analog design depends heavily on the properties of the materials used and on the physical shapes of the conductors and their proximity to each other

FIGURE 13.4 Trace resistance vs. trace width and thickness. (Prepared by Ritch Tech.)

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rather than on the ability to handle very large numbers of circuits simultaneously. Hand routing or connecting of the individual parts coupled with manipulating the shapes of individual copper features are essential parts of this design process. For these reasons, the design tools and design team must be chosen to meet these needs. Physical layout tools that provide convenient graphical manipulation of PCB shapes are a must.

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13.1.2 Characteristics of Digital-Based PCBs Compared to RF and analog PCBs, digital-based PCBs have complex interconnections, but are tolerant of rather wide feature size and materials variations.

They are characterized by very large numbers of components, often numbering in the hundreds and sometimes the thousands. Digital components often have large numbers of leads, as high as 400 or more. This high lead count stems from logic architectures that have data and address buses as wide as 128 bits or more. To connect PCBs with these wide data buses, digital systems often contain board-to-board connectors with as many as 1,000 pins. Digital circuits have increasingly fast edges and low propagation delays to achieve faster performance. Edge rates as fast as 1 ns are now encountered in devices destined for products as common as video games. Table 13.2 lists edge speeds of some commonly used logic families, edge rate being the time required for a logic signal to switch from one logic level to the other (switching speed). Propagation delays, the time required for a signal to travel through a device, are decreasing along with edge rates.

TABLE 13.2 Typical Logic Family Switching Speeds Logic family STD TTL ASTTL FTTL HCTTL 10KECL BICMOS 10KHECL GaAs Edge speed, ns 5.0 1.9 1.2 1.5 2.5 0.7 0.7 0.3 Critical length, in 14.5 5.45 3.45 4.5 7.2 2.0 2.0 0.86

These fast edges and short propagation delays lead to transmission line effects such as coupling, ground bounce, and reflections that can result in improper operation of the resulting PCB. Table 13.2 illustrates the degree to which a fast switching signal will couple into a neighboring line as a function of the edge-to-edge separation and the height of