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System-on-a-Package (SOP) The definition of SOP depends on what is considered to be a system. In fact, much of what is referred to today as an electronic system is in reality a subsystem, meaning that it does not perform an autonomous electronic function. Consequently, SOP has multiple definitions. For example, some consider a multiple number of logic and memory ICs in a single package as an SOP. On the other hand, if the SOP does not contain analog peripheral device drivers, one might argue that the package really doesn t contain a system. Additionally, complete systems usually contain passive devices in addition to the ICs. Passive devices are required to make systems work, and if an entire system is to be placed in a package, then the required passives must go in as well,3, 11 making it what is often referred to an MCM. Area array packaging is becoming an enabling technology for addressing the needs of customized SOP solutions in order to reduce size, weight, and pincount at the second level of interconnection.12 This type of packaging technology includes pin grid array (PGA), ball grid array (BGA), and chip-scale packages (CSP), with BGA playing the largest role, primarily

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The conclusion is your nal opportunity to make your point with your audience. A good conclusion accomplishes these goals.

Fine Lithography Large Die Expensive Fab Infrastructure Lower Yield / Higher Cost Complex Performance Challenges Reliability Challenges

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Inertial mass: The rst appearance of mass in an elementary physics course is in the famous equation F = ma. Inertial mass is a measure of the ability of a body to resist changes in motion. In the following, we denote inertial mass by m I . Passive gravitational mass: In newtonian theory, the force that a body feels due to a gravitational eld described by a potential is given by F = m . The mass m in this equation, which describes the reaction of a body to a given gravitational eld, is called passive gravitational mass. We denote it by m p . Active gravitational mass: This type of mass acts as the source of a gravitational eld.

FIGURE 4.3 Future trends of IC, packaging, and system technologies as envisioned by personnel of the Packaging Research Center at The Georgia Institute of Technology. (Drawing provided courtesy of the Packaging Research Center, the Georgia Institute of Technology.)

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because of its versatility. Compared to conventional leaded packages, BGA packages exhibit improved electrical performance due to a shorter distance between the IC and the solder balls, improved thermal performance by the use of thermal vias or heat dissipation through power and ground planes, reduced handling related lead damage, and increased manufacturing yields due to their self-alignment feature.13 In fact, BGA has been one of the biggest contributing factors to the proliferation of mobile phones and other wireless communication systems. However, even with the advantages created by area-array packaging, performance, reliability, and cost requirements are challenging currently available area-array electronic package design, primarily by because of materials issues14 Fig. 4.3 provides an overview of IC, packaging, and system trends that are anticipated for the year 2007 and beyond.

is that defects in copper plating frequently are not shown by this method. For example, Hull cell testing will not help in detecting dull plating, roughness, or pitting. The procedure starts with brass panel preparation, in the following order: 1. 2. 3. 4. Remove the plastic film. Treat with cathodic alkaline cleaner. Soak in 10 percent sulfuric acid. Rinse.

Repeat these steps until the panel is water-break free. Proceed with the Hull cell as follows: 1. 2. 3. 4. 5. Rinse with test solution. Fill to mark. Adjust temperature and agitation. Attach panel to negative terminal. Plate.

Agitation should be similar to tank operation that is, vigorous air bubbling for copper, gentle stirring for tin and tin-lead, and none for tin-nickel. Plate copper and nickel at 2 A and other metals at 1 A. The effects of bath adjustment, carbon treatment, dummy plating, and so on, are readily translated from the Hull cell to actual tank operations. See previous sections on metal plating for Hull cell results, and consult the supplier for test equipment.

Significant portions of this chapter are drawn from George Milad, Electroplating, Printed Circuits Handbook, 5th ed, Clyde Coombs (ed.), 2001, Chap. 29.

1. Rothschild, B. F., Solder Plating of Printed Wiring Systems, Proceedings of the Printed Circuit Plating Symposium, California Circuits Association, November 5 6, 1969, pp. 10 21, and November 12 13, 1968, pp. 61 65. 2. Jacky, G. F., Soldering Experience with Electroplated Bright Acid Tin and Copper, Circuit Technology Today, California Circuits Association, October 1974, pp. 49 74. 3. Davis, P. E., and Duffek, E. F., The Proper Use of Tin and Tin Alloys in Electronics, Electronic Packaging and Production, Vol. 15, No. 7, 1975. 4. Kilbury, R. G., Producing Buried Via Multilayers: Two Approaches, Circuits Manufacturing, Vol. 25, No. 4, 1985, pp. 30 49. 5. Foulke, D. G., Electroplaters Process Control Handbook, rev. ed., R. E. Krieger Publishing Company, 1975. 6. Langford, K. E., and Parker, J. E., Analysis of Electroplating and Related Solutions, 4th ed., R. Draper Ltd., 1971. 7. See Ref. 64, Chap. 7, Additives. 8. Nelson, J. A., Basic Steps for Cross Sectioning, Insulation/Circuits, 1977. 9. Wellner, P., and Nelson, J., High Volume Cross Sectional Evaluation of Printed Circuit Boards, IPCWC- 4B-1, 1981.

30.1 DIRECT METALLIZATION TECHNOLOGY*

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