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Since the paradigm for characterizing solders and reliability has been honed through the millennia-long use of Sn-Pb solder, the development cycle for Pb-free solder should be significantly streamlined On the other hand, the rapid changeover to Pb-free solder brings with it risks with regard to process effectiveness and control, as well as the longterm reliability of the end product These risks will require continuous reevaluations of the solder alloy choice, appropriate surface finishes, soldering conditions, materials compatibility (PWB, IC packages, and such), redefinition of solder volume requirements for reliable solder joint strength, and even some equipment changesAs a result, the Chap 45 on Solder Materials contains a detailed discussion of lead-free alloys and materials and offer several choices on materials and discussion of their characteristics.

Since nearly all the practical Pb-free alloy choices have a higher melting temperature, a requisite higher energy consumption and energy cost is associated with the new soldering materials Equipment changes needed for Pb-free processing will be discussed in Chaps 46 and 47 Also, as Pb-based solder will remain in use until at least 2010 as per RoHS, another likely mode of failure will be the inadvertent use of Pb-free solder with Pb d packages or Pb d solder with Pb-free packages Although there is some backward and forward compatibility in terms of solders, packages, and surface finishes, there are also some difficulties Some packages meant for use in the Pb d process will not tolerate the higher soldering temperatures associated with most Pb-free solders.

In the case of a Pb-free ball grid array (BGA) soldered with Pb d solder, or vice versa, it is already known that there will be a negative impact to the resultant solder joint reliability for the leading Pb-free candidate solders Increased tensile strength with increased brittleness is commonly reported for the tin-silver-copper system a leading replacement candidate China, Japan, and Korea have legislative initiatives taking shape that are similar to the EU s, WEEE, and RoHS directives This is the case for several US states also There is no escaping the fact that Pb-free soldering will be the mainstay of all future electronics interconnections..

To complicate the problem further, off-chip interconnects are beginning to contribute to the challenge of SOC integration What this means is that interconnects, and not the ICs, are dominating, and often limiting, the system performance and increasing its cost7 Consequently, there is mounting support for moving interconnects off the chip and onto the package8 431 System-on-a-Chip (SOC) There are many reasons why semiconductor manufacturers continue to push on-chip integration of a system9 The reason most often cited is that on-chip integration allows faster interconnection between circuit components simply because of the shorter distances involved However, it has been pointed out that this may not be the case for all designs For example, on a large digital IC running at a high clock frequency, a signal traveling on a global interconnection trace may take dozens of clock cycles to reach its destination.

In such a case, dividing the device into smaller dice and using high-density interconnects on a package substrate can actually be faster10 Another reason for continuing with on-chip system integration is to avoid the configuration of a multichip package (MCP) because, historically, packages containing a system composed of a multiple number of chips have been larger than those containing a single-chip system Although designers will continue to be pressured to integrate as much functionality onto a single chip as possible, there are many factors that must be considered when deciding if SOC is the right approach to the design of an electronic system Furthermore, as minimum geometries continue to shrink and chip sizes continue to increase due to the incorporation of additional functionality, a point may be reached where it becomes economically impractical, if not impossible, to fabricate SOC.

At this point, SOP may provide the only practical alternative to SOC Now that chip and package are starting to be codesigned, an opportunity exists to develop capabilities for designing the SOP solutions that would cost less and perform better than SOP solutions11 Figure 42 provides a list of some of the challenges that must be addressed if SOC is to become the standard approach to electronic system integration..

SOC Challenges Fundamental: latency, SiO2 insulation Process complexity SOC design and test Wafer fab costs and yields Intellectual property for integrated functions

SOP Challenges Design: High speed digital, optical analog, RF Large-area intelligent manufacturing, cost/yield Thermal management Testing and reliability High performance for low cost fab